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STLS2F01
High performance 64-bit superscalar
Features

MIPS(R)
Loongson 2F: microprocessor
Preliminary Data
64-bit superscalar architecture 900 MHz clock frequency Single/double precision floating-point units New streaming multimedia instruction set support (SIMD) 64 Kbyte instruction cache, 64 Kbyte data cache, on-chip 512 Kbyte unified L2 cache On chip DDR2-667 and PCI-X controller 4 W @ 900 MHz power consumption: - Best in class for power management - Voltage/frequency scaling - Stand-by mode support - L2 cache disable/enable option Leading edge 90 nm process technology 27x27 heat spreader flip-chip BGA package MIPS based instruction set (MIPS III compatible)
HFCBGA452 (27x27x2.9mm)
The memory hierarchy is composed by the first level of 64 Kbyte 4-way set associative caches for instructions and data, the second level of 512 Kbyte unified 4-way set associative cache and the memory management unit (MMU) with translation lookaside buffer (TLB). The Loongson microprocessor family is the outcome of a successful collaboration started in 2004 between STMicroelectronics and the Institute of Computing Technology, part of the Chinese Academy of Science. Loongson microprocessors were co-developed by STMicroelectronics and the Institute of Computing Technology to address all the applications requiring high level of performance and low power dissipation. Compared to the STLS2E02 processor, the STLS2F01 has an enhanced architecture providing higher performance, reduced power consumption, integrated DDR2 memory controller and PCI-X bus interface.

Description
The STLS2F01 is a MIPS based 64-bit superscalar microprocessor, able to issue four instructions per clock cycle among six functional units: two integer, two single/double-precision floating-point, one 64bit SIMD and one load/store unit. The micro architecture is organized with ninestage of pipeline and support of dynamic branch prediction. Table 1. Device summary
Part numbers STLS2F01
Package HFCBGA452 (27x27x2.9mm)
Packing Tray
May 2008
Rev 1
1/48
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STLS2F01
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 Interface signal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PCI bus interface signal components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DDR2 SDRAM interface signal components . . . . . . . . . . . . . . . . . . . . . . 10 Local bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Initialization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Test and control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Supply and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
I/O bus interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 3.2 3.3 3.4 3.5 3.6 PCI interface characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Host and agent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PCI bus arbitrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Local bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
DDR2 SDRAM controller interface description . . . . . . . . . . . . . . . . . . 21
4.1 4.2 4.3 4.4 4.5 DDR2 SDRAM controller features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DDR2 SDRAM read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DDR2 SDRAM write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DDR2 SDRAM parameter format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DDR2 SDRAM sample mode configuration . . . . . . . . . . . . . . . . . . . . . . . 34
5 6
Initialization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Contents
6.1 6.2 6.3 6.4
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Recommended operation environment . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1 7.2 Thermal resistivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Reflow temperature to time curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8
Pin arrangement and package information . . . . . . . . . . . . . . . . . . . . . 43
8.1 Pin arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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List of tables
STLS2F01
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PCI bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DDR2 SDRAM controller interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Local bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Initialization interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 JTAG interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Processor internal/external frequency configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DDR internal/external frequency division factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Supply and GND signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DDR SDRAM configuration parameter register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Absolute maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Recommended operating temperature, voltage supply and frequency . . . . . . . . . . . . . . . 37 DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC parameters (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Clock parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Input setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Input setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Output delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 JTAG parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reflow temperature parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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STLS2F01
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Interface signal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 STLS2F01 uniprocessor system connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STLS2F01 multiprocessor system connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Local bus read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Local bus write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DDR2 SDRAM read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DDR2 SDRAM write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Initialization process when in main bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Reflow temperature to time curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Pin arrangement (left-hand side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Pin arrangement (middle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Pin arrangement (right-hand side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 HFCBGA452 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Introduction
STLS2F01
1
Introduction
STLS processors are based on the Loongson CPU architecture licensed by STMicroelectronics from the Institute of Computing Technology (ICT), which is part of the Chinese Academy of Science. The STLS family belongs to the 64-bit high-end processors for applications requiring high level of performance and efficiency in terms of cost, power consumption and area. Loongson CPU architecture is compatible in user mode at the MIPS III level of the MIPS 64-bit architecture. This microprocessor achieves one of the top positions in the MIPS family for the combination of multiple features: high clock frequency, out-of-order superscalar execution and ability to run single-instruction-multiple data (SIMD). STLS processors implement a superscalar, out-of-order execution pipeline with dynamic branch prediction and non-blocking cache.
Figure 1.
Block diagram
Commit Bus Branch Bus Reorder Queue BRQ BTB ROQ D-Cache 64KB TAG Compare TLB DDR2 Controller 333MHz DDR CP0 Queue Writeback Bus
PC + 16
Map Bus Register Mapper Fix RS Integer Register File ALU1 ALU2 AGU Float RS Floating Point Register File FPU1 FPU2
Pre-Decoder Refill Bus
BHT PC
ITLB
I-Cache 64KB
Decoder
Miss Writeback Cache Interface Queue Queue
L2 cache
I/O Controller
AXI Crossbar
133MHz PCI-X Local IO GPIO, INT
AC00117
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STLS2F01
Introduction The instruction pipeline allows to fetch and code four instructions per cycle and dynamically issue the decoded instructions to five fully pipe lined function components. The STLS2F01 uses out-of-order execution and aggressive memory hierarchy design to maximize pipeline efficiency. Out-of-order execution is accomplished with a combination of register renaming, dynamic scheduling, and branch prediction techniques. The result is fewer pipeline stalls caused by WAR (write after read) and WAW (write after write) hazards, RAW (read after write) hazards, and control hazards. The STLS2F01 has a 64-entry physical register file for fixed- and floating-point register renaming, a 16-entry fixed-point reservation station, and a 16-entry floating-point reservation station that is responsible for out-of-order instruction issuing. A 64entry ROQ (reorder queue) ensures that out-of-order executed instructions are committed in the program order. For precise branch prediction, a 16-entry branch target buffer (BTB), a 4K-entry branch history table (BHT), a 9-bit global history register (GHR), and a 4-entry return address stack (RAS) are used to record branch history information. The STLS2F01 memory hierarchy is also engineered for high performance. There is a 64 Kbyte instruction cache, a 64 Kbyte data cache, and a 512 Kbyte level-two cache. All four-way set associative. The on-chip DDR memory allows the STLS2F01 to achieve high memory bandwidth with low latency. The fully associative translation lookaside buffer (TLB) has 64 entries, each mapping an odd and even page. A 24-entry memory access queue contains a content-addressable memory for dynamic memory disambiguation and allows the STLS2F01 to implement out-of-order memory access, non-blocking cache, load speculation, and store forwarding. The STLS2F01 has two fixed-point functional units, two floating-point functional units, and one memory access unit. The floating-point units can also execute 32- or 64-bit fixed-point instructions and 8- or 16-bit SIMD fixed-point instructions through extension of the fmt field of the floating-point instructions. The SIMD unit extends the STLS2E02 with new XX SSE2 type instructions. The basic pipeline stages of the STLS2F01 include instruction fetch, pre-decode, decode, register rename, dispatch, issue, register read, execution, and commit. The STLS2F01 device is manufactured in ST 90 nm CMOS technology. The STLS2F01 is an evolution of the STLS2E02 with enhanced I/O and memory accessing bandwidth and a software working frequency changing scheme. The STLS2F01 has a standard 32-bit PCI/PCI-X interface, a standard 64-bit DDR2 interface, an 8/16-bit local I/O interface, a 4-bit GPIO interface. The STLS2F01 achieves a higher memory access bandwidth by utilizing a 64-bit DDR2 memory controller. Compared to its predecessor, the STLS2F01 provides better power management ability by using a software manageable working frequency changing scheme. The operating system can utilize this feature to change the processor frequency according to the workload. The STLS2F01 integrates a video accelerate module in its write data path to the PCI/PCI-X controller. Coupled with software drivers, the video accelerate module can transfer YUV format video data to RGB format and zoom automatically. This greatly reduces the processor's workload when the system utilizes a simple VGA controller. The cores are centered on 2x2 AXI cross bar with 128-bit width data bus. The CPU core and PCI/PCI-X slave takes up two master ports, DDR2 controller one slave port, and all other modules including the PCI/PCI-X master share one slave port.
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Interface description
STLS2F01
2
2.1
Interface description
Interface signal block diagram
The STLS2F01's interface signals are showed in Figure 2. Note: The arrow indicates signal directions, e.g. input, output or bidirectional. Figure 2. Interface signal block diagram
PCI AD[31:0] PCI CBEn[3:0] P C I I N T E R F A C E S I G N A L S PCI REQ [6:1] PCI GNT [6:1] PCI REQ [0] PCI GNT [0] PCI PAR INTn [3:0] PCI PERR PCI IRQn [3:0] PCI SERR GPIO [3:0] PCI FRAMEn PCI IRDYn TCK PCI TRDYn TDI PCI DEV SELn TDO PCI STOPn TMS PCI ID SEL TRST L O C A L B U S S I G N A L S LIO AD [15:0] LIO A [7:0] LIO C Sn LIO ROMC Sn LIO WRn LIO RDn LIO ADLOCK LIO DIR LIO DEN J T A G SYSCLK MEMCLK CLKSEL [9:0] TESTCLK PCI CLK I N T E R R U P T C L O C K
NMIn
Loongson2F
DDR2 DQ[63:0] DDR2 CB[7:0] DDR2 DQ Sp[8:0] DDR2 DQ Sn[8:0] DDR2 A[14:0] DDR2 DQM[8:0] DDR2 CKp[5:0] DDR2 CKn[5:0] DDR2 CKE[3:0] D D R 2 S D R A M I N T E R F A C E S I G N A L S
I N I T T E S T & C O N T R O L
SYSRESETn PCI RESETn PCI CONFIG [7:0]
DDR2 ODT[3:0] DDR2 SC Sn[3:0] DDR2 BA[2:0] DDR2 RASn DDR2 CASn
TEST CTRL [7:0] PLLCLOCK0 PLLCLOCK1
DDR2 WEn DDR2 GATEO[3:0] DDR2 GATEI[3:0]
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STLS2F01
Interface description
2.2
PCI bus interface signal components
The STLS2F01's PCI bus signal includes:

32-bit address data bus 4-bit command data ID bus 14-bit bus arbitrator 7-bit interface control 2-bit error report signals
The STLS2F01's PCI bus signals are listed in Table 2. Table 2.
Name PCI_AD[63:0] PCI_CBEn[7:0] PCI_PAR PCI_REQn[6:1] PCI_REQn[0] PCI_GNT[6:1] PCI_GNT[0] PCI_FRAMEn PCI_IRDYn PCI_TRDYn PCI_STOPn PCI_DEVSELn
PCI bus signals
Input/output I/O I/O I/O I I/O O I/O I/O I/O I/O I/O I/O PCI address/data bus PCI command/byte Address/data parity check signal External Request External request input/request output to external arbiter PCI bus grant to external device PCI bus grant to external device / grant input from external arbiter PCI bus cycle frame PCI initiator ready PCI target ready PCI stop PCI device select Description
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Interface description
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2.3
DDR2 SDRAM interface signal components
The STLS2F01 includes a built-in memory controller fully compatible with DDR2 SDRAM industry standard (JESD79-2B). These signals include:

72-bit bidirectional data bus (ECC included) 9-bit bidirectional data strobe differential signal (ECC included) 9-bit data mask signal (ECC included) 15-bit address bus 7-bit bank and chip select signal 6-bit differential clock 4-bit clock enable 3-bit command bus 4-bit delay sample input/output signal 4-bit ODT (on die termination) signal
The STLS2F01 DDR2 SDRAM controller signals are listed in Table 3. Table 3.
Name DDR2_DQ[63:0] DDR2_CB[7:0] DDR2_DQSp[8:0] DDR2_DQSn[8:0] DDR2_DQM[8:0] DDR2_A[14:0] DDR2_BA[2:0] DDR2_WEn DDR2_CASn DDR2_RASn DDR2_SCSn[3:0] DDR2_CKE[3:0] DDR2_CKp[5:0] DDR2_CKn[5:0] DDR2_GATEI[3:0] DDR2_GATEO[3:0] DDR2_ODT[3:0]
DDR2 SDRAM controller interface signals
Input/output IO IO IO IO O O O O O O O O O O I O O Description DDR2 SDRAM data bus DDR2 SDRAM data ECC data bus DDR2 SDRAM data strobe (ECC included) DDR2 SDRAM data strobe (ECC included) DDR2 SDRAM data mask (ECC included) DDR2 SDRAM address bus DDR2 SDRAM bank address signal DDR2 SDRAM write enable DDR2 SDRAM column select enable DDR2 SDRAM row select enable DDR2 SDRAM chip select DDR2 SDRAM clock enable DDR2 SDRAM phase clock output DDR2 SDRAM phase inversion clock output DDR2 SDRAM delay sample input signal DDR2 SDRAM delay sample output signal DDR2 SDRAM on-die termination signal
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STLS2F01
Interface description
2.4
Local bus signals
The local bus provides a simple bus interface for system boot ROM and I/O device. The interface is designed for chip-connect simplicity. The local bus signals are listed in Table 4. Table 4.
Name LIO_AD[15:0] LIO_A[7:0] LIO_CSn LIO_ROMCSn LIO_WRn LIO_RDn LIO_ADLOCK LIO_DIR LIO_DEN
Local bus signals
Input/output I/O O O O O O O O O Description Local I/O address and data bus When ADLOCK valid output the most significant 16 bits Lowest significant 8-bit address bus Local I/O chip select Local I/O ROM chip select Local I/O write enable Local I/O read enable Local I/O address lock Local I/O direction Local I/O device enable
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Interface description
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2.5
Initialization signals
Table 5 provides the names, definitions, and directions and descriptions of the initialization signals. Table 5.
Name SYSRESETn PCI_RESETn
Initialization interface signals
Input/output I I/O Description System reset. Low state of the signal must be maintained more than one SYSCLK period. It can be asynchronous to SYSCLK. PCI interface reset. PCI Configuration 7 undefined 6:5 PCI-X bus speed selection 4 PCI-X bus mode 3 Master mode 2 Start from PCI 1 External PCI arbitration 0 16-bit starting ROM Note: 6 0 0 1 1 5 0 1 0 1 4 0 1 1 1 PCI-X BUS mode PCI 33/66 PCI-X 66 PCI-X 100 PCI-X 133
PCI_CONFIG
I
The STLS2F01 processor includes two reset signals: SYSRESETn and PCI_RESETn.
SYSRESETn: This reset signal is the only way to reset whole STLS2F01 processor. SYSCLK and MEMCLK must provide stable clock when SYSRESETn is valid. The width of SYSRESETn should be more than one clock period. Internal reset-control begins to reset internal logic when reset signal is invalid. The internal reset will be finished after 64K SYSCLK cycle. Then reset exception vector could be executed PCI_RESETn: This signal works as output when the processor works as a system main bridge. And the reset of PCI-X devices in the system must be controlled by the signal. When the processor works as PCI/PCI-X devices used in other system, the signal works as input to reset the PCI interface of processor. (Note: Resetting PCI interface when process is running may cause the processor stop working)
PCI_CONFIG: defines the mode of working of the processor interface. It must keep stable during system reset, so that software could read this value from internal register after system started. The PCI address of the first instruction is 0x1fc00000 when system starting from PCI is configured. Otherwise the first instruction will be fetched from address 0 of Local Bus ROM.
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STLS2F01
Interface description
2.6
Interrupt signals
The STLS2F01 processor supports up to 12 external interrupts and one non-maskable interrupt (NMI). There are 4 PCI interrupt signals, 4 special interrupt signals and 4 configurable GPIO interrupt. In addition, there are 3 internal interrupts, two PCI bus error report signals and one DDR2 control interrupt. When an interrupt takes place, the processor handles the exception. Table 6 shows the names, definitions, directions and descriptions of the interrupt signals. Table 6.
Name INTn[3:0]
Interrupt interface signals
Input/output I Description 4 external interrupt signals. OR operations are performed on these signals with interrupt register from bit 5 to bit 2 separately. NMI. An OR operation is performed on the NOT-value of this signal and the interrupt register's 6th bit. These interrupts should be enabled in the interrupt controller and can be configured as different active power level and different trigger mode. These interrupts could be routed to interrupt register bit 0/1. These interrupts should be enabled in the interrupt controller and low active. These interrupts could be routed to interrupt register bit 0/1. PCI bus parity error, high pulse active. These interrupts could be routed to interrupt register bit 0/1. PCI bus error, high pulse active. These interrupts could be routed to interrupt register bit 0/1.
NMIn
I
GPIO[3:0]
I/O
PCI_IRQ[3:0]
I
PCI_PERR PCI_SERR
I/O I/O
2.7
JTAG signals
The STLS2F01 provides a JTAG-compliant boundary scan interface. The JTAG interface is particularly suitable for testing the processor pins for connectivity. The Table 7 provides the names, definitions, directions and descriptions of the JTAG signals. Table 7.
Name TDI TDO TMS TCK
JTAG interface signals
Input/output I O I I Description JTAG serial scan data input JTAG serial scan data input JTAG Command, indicating that the input serial data is a command. TAG serial scan clock
2.8
Test and control signals
On the STLS2F01 chip, the test signals are only used for chip physical test, e.g. scan chain test. When the chip works normally, these signals are set invalid 1.
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Interface description
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2.9
Clock signals
For information about clock on the STLS2F01 chip, see Table 8. The processor has three system input clock signals. (SYSCLK, MEMCLK and PCI_CLK) The TESTCLK is only used for chip test. The CPU core clock and DDR2 control clock are generated separately by PLL using SYSCLK and MEMCLK. The frequency division is controlled by CLKSEL. For more about the division factor, see Table 9 and Table 10. Table 8. Clock signals
Name SYSCLK Input/output I Description System input clock, which drives the built-in PLL to generate core clock. It also used as clock of system reset circuit. DDR2 controller input clock, which is used by the built-in PLL to generate DDR2 control clock. PLL frequency division control signal of core clock, see
MEMCLK CLKSEL[4:0] CLKSEL[9:5] PCI_CLK
I I I I
Table 9.
PLL frequency division control signal of DDR2 controller clock, see Table 10. Clock for PCI and Local bus interface.
Table 9.
Processor internal/external frequency configuration
Multi. factor 1 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.5 5 5.5 6 Input frequency range (MHz) 88.9~177.8 80.0~160.0 72.7~145.5 66.7~133.3 61.5~123.1 57.1~114.3 53.3~106.7 50.0~100.0 88.9~177.8 80.0~160.0 72.7~145.5 66.7~133.3 01100 01101 01110 01111 00000 00001 00010 00011 00100 00101 00110 00111 6.5 7 7.5 8 9 10 11 12 13 14 15 16 61.5~123.1 57.1~114.3 53.3~106.7 50.0~100.0 88.9~177.8 80.0~160.0 72.7~145.5 66.7~133.3 61.5~123.1 57.1~114.3 53.3~106.7 50.0~100.0 CLKSEL[4:0] Multi. factor Input frequency range (MHz)
CLKSEL[4:0] 11xxx 10000 10001 10010 10011 10100 10101 10110 10111 01000 01001 01010 01011
14/48
STLS2F01 Table 10. DDR internal/external frequency division factor
Multi. factor 1.125 1.25 1.375 1.5 1.625 1.75 1.875 2 2.25 2.5 2.75 3 Input frequency range (MHz) 88.9~177.8 80.0~160.0 72.7~145.5 66.7~133.3 61.5~123.1 57.1~114.3 53.3~106.7 50.0~100.0 88.9~177.8 80.0~160.0 72.7~145.5 66.7~133.3 CLKSEL[9:5] 10100 10101 10110 10111 01000 01001 01010 01011 01100 01101 01110 01111 00xxx Multi. factor 3.25 3.5 3.75 4 4.5 5 5.5 6 6.5 7 7.5 8 1
Interface description
CLKSEL[9:5] 11000 11001 11010 11011 11100 11101 11110 11111 10000 10001 10010 10011
Input frequency range (MHz) 61.5~123.1 57.1~114.3 53.3~106.7 50.0~100.0 88.9~177.8 80.0~160.0 72.7~145.5 66.7~133.3 61.5~123.1 57.1~114.3 53.3~106.7 50.0~100.0 -
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Interface description
STLS2F01
2.10
Supply and ground
See Table 11 for supply and GND signals at the STLS2F01. Table 11.
Name vdd gnd Vdde1v8 gnde Vdde3v3 DDR2_VREF pll_vdd_1 pll_gnd_1 pll_vdd_0 pll_gnd_0 Pllio_vdde1v8 pllio_gnde pllio_vdd pllio_gnd Pll_vdde1v8_1 Pll_gnde_1 Pll_vdde1v8_0 Pll_gnde_0 comp1v8_gnd comp1v8_resistor
Supply and GND signals
Input/output PWR GND PWR GND PWR I PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND GND I Description 1.2 V CPU core voltage 1.2 V CPU core ground 1.8 V DDR2 power supply 1.8 V DDR2 and 3.3V I/O ground 3.3 V IO power supply 0.9 V DDR reference voltage input 1.0 V PLL 1 digital power supply 1.0V PLL 1 digital ground 1.0V PLL 0 digital power supply 1.0V PLL 0 digital ground 1.8V PLL I/O power supply 1.8V PLL I/O ground 1.2V PLL I/O power Supply 1.2V PLL I/O ground 1.8V PLL 1 analog power supply 1.8V PLL 1 analog ground 1.8V PLL 0 analog power supply 1.8V PLL 0 analog ground Compensation reference current ground Compensation external resistor input
16/48
STLS2F01
I/O bus interface description
3
I/O bus interface description
The STLS2F01 processor I/O interface consists of PCI bus and Local bus. PCI bus is used to for generic peripheral devices interface, while Local bus is the simple interface to boot or debug the processor.
3.1
PCI interface characteristic
The PCI interface features:

PCI 2.3 and PCI-X 1.0 compatible Support PCI 66 MHz and PCI-X133 MHz Support dual address cycle for 64-bit addressing Support 8 outstanding master request in PCI-X mode Support 4 delay-split read request in PCI-X mode
3.2
Host and agent mode
The STLS2F01's PCI interface could be worked in Host mode or Agent mode. It depends on initial signal PCI_CONFIG. When the processor works in Host mode, the interface initializes the bus device according to the value of PCI_CONFIG[6:4]. In this case, PCI_IDSEL could connect to GND directly. When the processor works in Agent mode, the initial value of PCI bus defines the work-mode of the interface. In Host mode, on the system main board, the value of PCI_CONFIG[6:4] should be set according to the ability of bus device. (Please refer to PCI-X 1.0 standard)
3.3
PCI bus arbitrator
PCI/PCI-X bus arbitrator built in STLS2F01 supports 7 external masters at most. The arbitration rules are two levels Round Robin scheduling. The level of each request is determined by software configuration. The bus is granted to insert a dummy cycle during switching. Bus parking can be configured as the last master or any specified master. The internal request/grant wire of interface could be set to connect to the number 0 request/grant wire by PCI_CONFIG [1], so that the external bus arbitrator can be used.
3.4
System interface connection
The STLS2F01 processor can be easily implemented in uniprocessor system. Since no multi-processor cache coherence protocol is supported in PCI interface, the cache coherence should be managed by software in multiprocessor system.
Single processor system connection
17/48
I/O bus interface description Figure 3. STLS2F01 uniprocessor system connection
STLS2F01
PCI Dev
PCI Dev
PCI Dev
PCI Bus PCI_REQ PCI_GNT Loongson2F
Boot Rom
Local Bus
Multiprocessor system connections
Figure 4.
STLS2F01 multiprocessor system connections
PCI_REQn PCI_GNTn Loongson2F PCI Bus I/O Chipset PCI_REQn PCI_GNTn Loongson2F PCI Bus
3.5
Local bus description
Local bus is a simple peripheral interface. It's mainly used to connect to boot ROM. There are two chip select signals, and corresponding configurable data width and access delay.
18/48
STLS2F01
I/O bus interface description The read and write timing are shown in the Figure 5 and Figure 6. When the data width is 16-bit, the output address can be generated by shifting the physical address right one bit.
Figure 5.
Local bus read timing
pciclk
lioden
liodir
lioaddr
addr[7:0]
addr[7:0]+1
lioad
addr[23..8]
data
data
lioadlock
liocs
liord
.
19/48
I/O bus interface description Figure 6. Local bus write timing
pciclk
STLS2F01
lioden
liodir
lioaddr
addr[7:0]
addr[7:0]+1
lioad
addr[23:8]
data_0
data_1
lioadlock
liocs
liowr
3.6
Interrupt handling
An interrupt controller is built in STLS2F01 processor to handle internal and external interrupt. The most significant 4 bits of the interrupt INTn[5:0] in STLS2E01 are still being used as interrupt in STLS2F01, while the other two bits are used for new interrupt in STLS2F01, such as PCI_IRQ and GPIO, etc. How to handle the interrupt between processors: the interrupt initiator writes the dedicated interrupt register in the chipset. Upon receiving the request for interrupt transmission, the chipset will request the target processor for interrupt. The processor handles the request in the same way as the previous STLS2E01 and beyond.
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STLS2F01
DDR2 SDRAM controller interface description
4
DDR2 SDRAM controller interface description
The STLS2F01 integrates a built-in memory controller compliant with DDR2 SDRAM standard (JESD79-2B). The STLS2F01 provide JESD79-2B-compliant read/write operations onto memory.
4.1
DDR2 SDRAM controller features
The STLS2F01 CPU supports up to 4 physical memory by using two DDR SDRAM chip select signals, with a 18-bit address bus (15-bit row/column address and 3-bit logic bank bus). The maximum address space is 128GB (237 bytes). This device supports all the JESD79-2B-compatible memory chips. The DDR2 controller parameters can be set to support specific memory chip type. The maximum number of chip selection (CS_n) is 2-bit. The maximum width of row address (RAS_n) is 15-bit, and the maximum width of column address (CAS_n) is 14-bit. And there is 3-bit logic bank bus (BANK_n). For example, in the 4GB address space configuration of 2-bit CS_n, 3-bit BANK_n, 12-bit RAS_n and 12-bit CAS_n, the physical memory address CPU required can be translated into row/column address as shown in the DDR2 SDRAM row/column address translation paragraph.
DDR2 SDRAM row/column address translation
36 32 31 CS_n 5 2 30 29 RAS_n 12 18 17 15 14 CAS_n 12 32 0
BANK_n 3
Byte_enable 3
The built-in memory controller IC receives only memory read/write requests from a processor or external device. The controller IC is in Slave state whenever memory are read or written. A dynamic page management policy is implemented on the integrated memory controller. For one access to memory, the controller selects Open Page/Close Page strategies on a hardware circuit, without software designers' intervention. The memory controller features:

Full pipeline support to command and read/write data of interface Increasing bandwidth by merging and sorting memory command Modify fundamental parameters through the configuration of register read/write ports Built-in delay compensation circuit (DCC), it is used to send/receive data reliably 1-bit and 2-bit error detection, 1-bit error correction by error correcting-code (ECC) Frequency: 133 MHz - 333 MHz
4.2
DDR2 SDRAM read protocol
As showed in Figure 7 DDR2 SDRAM read protocol, the command (CMD) includes RAS_n, CAS_n and WE_n. When a read request happens, RAS_n=1,CAS_n=0,and WE_n=1.
21/48
DDR2 SDRAM controller interface description Figure 7. DDR2 SDRAM read protocol CAS latency = 3, read latency = 3, burst length = 8
T0 T1 T2 T3 T4 T5 T6 T7
STLS2F01
T8
CK/CK
CMD
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS/DQS
CL=3 RL=3
DQS
DOUTA1
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
4.3
DDR2 SDRAM write protocol
As showed in Figure 8 DDR2 SDRAM write protocol, the command (CMD) includes RAS_n, CAS_n and WE_n. When a write request happens, RAS_n=1, CAS_n=0,and WE_n=0. Unlike a read transaction, DQM is used to identify the write mask. In other words, the number of written bytes is needed. DQM is synchronous with DQS.
Figure 8.
DDR2 SDRAM write protocol CAS latency = 3, write latency = read latency = 2, burst length = 4
T0 T1 T2 T3 T4 T5 T6 T7 Tn
CK/CK
CMD
WRITE A
NOP
NOP
NOP
NOP
NOP Completion of the Burst Write
Precharge
NOP
Bank A Activate
tDQS6
DQS/DQS
WL = RL - 1 = 2 WR tRP
DQS
DINA0
DINA1
DINA2
DINA3
22/48
STLS2F01
DDR2 SDRAM controller interface description
4.4
DDR2 SDRAM parameter format
Since different DDR2 SDRAMs may be used in the system, DDR2 SDRAM needs configuration after power-on reset. The JESD79-2B standard defines detailed configuration operation and process. DDR2 is not available before the memory is initialized. Memory initialization sequence: 1. 2. 3. 4. System reset, aresetn signal is set 0, all registers content will be initial value. System reset release, aresetn signal is set 1. Issue 64-bit write command to configuration register, all 29 registers are configured. If register CTRL_03 is written in this step, the parameter of start should be set 0. Issue 64-bit write command to register CTRL_03. Set the parameter of start to 1. Then, memory controller will send initial instruction to memory automatically.
In the STLS2F01 processor design, after the system motherboard is initialized, the DDR2 SDRAM controller needs configure memory type before the memory is used. Specifically, corresponding configuration parameters are written into the 29 64-bit registers corresponding to the physical address 0x0000 0000 0FFF FE00. In one register, one, multiple or partial parameter data can be included. The configuration register and its parameters are shown in Table 12 Note: the bits not used are all reserved bits. Table 12. DDR SDRAM configuration parameter register format
Parameters Bits Default value Range Description
CONF_CTL_00[31:0] Offset: 0x00 AREFRESH 24:24 0x0
DDR2 667:0x00000101 0x0-0x1 Initiate auto-refresh when specified by AUTO_REFRESH_MODE. Writeonly Enable auto pre-charge mode of controller. Enable address collision detection for command queue placement logic. Enable command aging in the command queue, avoiding low priority command hungry.
AP ADDR_CMP_EN
16:16 8:8
0x0 0x0
0x0-0x1 0x0-0x1
ACTIVE_AGING
0:0
0x0
0x0-0x1
CONF_CTL_00[63:32] Offset: 0x00 DDR2_SDRAM_MODE 56:56 0x0
DDR2 667:0x01000100 0x0-0x1 DDRI or DDRII mode. Allow controller to issue command to other banks while a bank is in auto pre-charge. Note: most DDR2 DIMM vendor do not support this feature. Enable bank splitting for command queue placement logic. Sets if auto-refresh will be at next burst or next command boundary.
CONCURRENTAP
48:48
0x0
0x0-0x1
BANK_SPLIT_EN AUTO_REFRESH_MODE
40:40 32:32
0x0 0x0
0x0-0x1 0x0-0x1
CONF_CTL_01[31:0] Offset: 0x10
DDR2 667:0x00010000
23/48
DDR2 SDRAM controller interface description Table 12.
STLS2F01
DDR SDRAM configuration parameter register format (continued)
Parameters Bits Default value 0x0 Range Description Disable auto-corruption of ECC when un-correctable errors occur in R/M/W operations. Single-ended or differential DQS pins. Enable the DLL bypass feature of the controller. Status of DLL lock coming out of master delay. Read-only.
ECC_DISABLE_W_UC_ERR
24:24
0x0-0x1
DQS_N_EN DLL_BYPASS_MODE DLLLOCKREG
16:16 8:8 0:0
0x0 0x0 0x0
0x0-0x1 0x0-0x1 0x0-0x1
CONF_CTL_01[63:32] Offset: 0x10 FWC 56:56 0x0
DDR2 667:0x00100000 0x0-0x1 Force a write checks. Xor XOR_CHECK_BITS with ECC code and write to memory. Write-only Sets when write command are issued to DRAM device. Allows user to interrupt memory initialization to enter self-refresh mode. Number of banks on the DRAM(s).
FAST_WRITE
48:48
0x0
0x0-0x1
ENABLE_QUICK_SREFRESH EIGHT_BANK_MODE
40:40 32:32
0x0 0x0
0x0-0x1 0x0-0x1
CONF_CTL_02[31:0] Offset: 0x20 NO_CMD_INIT 24:24 0x0
DDR2 667:0x00000000 0x0-0x1 Disable DRAM command until TDLL has expired during initialization. Allow the controller to interrupt a combined write command with auto pre-charge with another write command. Allow the controller to interrupt a combined read with auto pre-charge command with another read command. Allow the controller to interrupt an auto pre-charge command with another command.
INTRPTWRITENA
16:16
0x0
0x0-0x1
INTRPTREADA
8:8
0x0
0x0-0x1
INTRPTAPBURST CONF_CTL_02[63:32] PRIORITY_EN POWER_DOWN PLACEMENT_EN
0:0
0x0
0x0-0x1
Offset: 0x20 56:56 48:48 40:40 0x0 0x0 0x0
DDR2 667:0x01000101 0x0-0x1 0x0-0x1 0x0-0x1 Enable priority for command queue placement logic. Disable clock enable and set DRAMs in power-down state. Enable placement logic for command queue. Enable extra turn-around clock between back-to-back reads/writes to different chip selects.
ODT_ADD_TURN_CLK_EN
32:32
0x0
0x0-0x1
24/48
STLS2F01 Table 12.
DDR2 SDRAM controller interface description DDR SDRAM configuration parameter register format (continued)
Parameters CONF_CTL_03[31:0] RW_SAME_EN REG_DIMM_EN REDUC PWRUP_SREFRESH_EXIT CONF_CTL_03[63:32] Bits Offset: 0x30 24:24 16:16 8:8 0:0 0x0 0x0 0x0 0x0 Default value Range Description
DDR2 667:0x01000000 0x0-0x1 0x0-0x1 0x0-0x1 0x0-0x1 Enable read/write grouping for command queue placement logic. Enable registered DIMM operation of the controller. Enable the half data path (32-bit) feature of the controller. Power-up via self-refresh instead of full memory initialization.
Offset: 0x30
DDR2 667:0x01010000 Enable command swapping logic between commands of the same type from the same port in execution unit. Enable command swapping logic in execution unit. Initiate command processing in the controller. Place DRAMs in self-refresh mode.
SWAP_PORT_RW_SAME_EN
56:56
0x0
0x0-0x1
SWAP_EN START SREFRESH CONF_CTL_04[31:0]
48:48 40:40
0x0 0x0
0x0-0x1 0x0-0x1 0x0-0x1
32:32 0x0 Offset: 0x40 24:24 0x0
DDR2 667:0x00010101 0x0-0x1 Write EMRS data to the DRAMs. Write-only. Allow controller to interrupt write bursts to the DRAMs with a read command. Issue self-refresh commands to the DRAMs every TREF cycle. Allow the controller to execute auto pre-charge commands before TRAS_MIN expires.
WRITE_MODEREG
WRITEINTERP
16:16
0x0
0x0-0x1
TREF_ENABLE
8:8
0x0
0x0-0x1
TRAS_LOCKOUT CONF_CTL_04[63:32] RTT_0
0:0 Offset: 0x40 57:56
0x0
0x0-0x1
DDR2 667:0x01000202 0x0 0x0-0x3 On-Die termination resistance setting for all DRAM devices. ECC error checking and correcting control. 2'b00 - no ECC 2'b01 - report error only, not corrected 2'b10 - no ECC device used 2'b11 - report and correct ECC error Priority of write command from port 0.
CTRL_RAW
49:48
0x0
0x0-0x3
AXI0_W_PRIORITY
41:40
0x0
0x0-0x3
25/48
DDR2 SDRAM controller interface description Table 12.
STLS2F01
DDR SDRAM configuration parameter register format (continued)
Parameters Bits 33:32 Default value 0x0 Range 0x0-0x3 Description Priority of read command from port 0.
AXI0_R_PRIORITY CONF_CTL_05[31:0]
Offset: 0x50 26:24 0x0
DDR2 667:0x04050202 0x0-0x7 Difference between number of column pins available and number being used. Encoded CAS latency sent to DRAMs during initialization. Difference between number of address pins available and number being used. Set termination resistance in controller pads.
COLUMN_SIZE
CASLAT
18:16
0x0
0x0-0x7
ADDR_PINS
10:8
0x0
0x0-0x7
RTT_PAD_TERMINATION CONF_CTL_05[63:32] Q_FULLNESS PORT_DATA
1:0
0x0
0x0-0x3
Offset: 0x50 58:56 0x0
DDR2 667:0x00000000 0x0-0x7 Quantity that determines command queue full.
_ERROR_TYPE
50:48
0x0
0x0-0x7
Type of error and access type that caused the PORT data error. Readonly. bit 0 - data overflow. The write data quantity exceeded the Maximum_Byte_Request configured option. bit 1 - write data interleaved beyond supported interleaving depth. bit 2 - ECC 2-bit error. Type of command that caused and Out-of-Range interrupt. Read-only. Maximum number of chip selects available. Read-only
OUT_OF_RANGE_TYPE MAX_CS_REG CONF_CTL_06[31:0] TRTP TRRD TEMRS TCKE CONF_CTL_06[63:32] APREBIT WRLAT TWTR TWR_INT
42:40 34:32
0x0 0x4
0x0-0x7 0x0-0x4
Offset: 0x60 26:24 18:16 10:8 2:0 Offset: 0x60 59:56 50:48 42:40 34:32 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
DDR2 667:0x03040203 0x0-0x7 0x0-0x7 0x0-0x7 0x0-0x7 DRAM TRTP parameter in cycles. DRAM TRRD parameter in cycles. DRAM TEMRS parameter in cycles. Minimum CKE pulse width.
DDR2 667:0x0a040305 0x0-0xf 0x0-0x7 0x0-0x7 0x0-0x7 Location of the auto pre-charge bit in the DRAM address. DRAM WRLAT parameter in cycles. DRAM TWTR parameter in cycles. DRAM TWR parameter in cycles.
26/48
STLS2F01 Table 12.
DDR2 SDRAM controller interface description DDR SDRAM configuration parameter register format (continued)
Parameters CONF_CTL_07[31:0] ECC_C_ID CS_MAP CASLAT_LIN_GATE Bits Default value Range Description DDR2 667:0x000f090a 0x0-0xf 0x0-0xf 0x0-0xf Source ID associated with correctable ECC event. Read-only Number of active chip selects used in address decoding. Adjusts data capture gate open by half cycles. Sets latency from read command send to data receive from/to controller.
Offset: 0x70 27:24 19:16 11:8 0x0 0x0 0x0
CASLAT_LIN CONF_CTL_07[63:32] MAX_ROW_REG MAX_COL_REG INITAREF ECC_U_ID CONF_CTL_08[31:0]
3:0 Offset: 0x70 59:56 51:48 43:40 35:32 Offset: 0x80
0x0
0x0-0xf
DDR2 667:0x00000400 0xf 0xe 0x0 0x0 0x0-0xf 0x0-0xe 0x0-0xf 0x0-0xf Maximum width of memory address bus. Read-only Maximum width of column address in DRAMs. Read-only Number of auto-refresh command to execute during DRAM initialization. Source ID associated with the uncorrectable ECC even. Read-only.
DDR2 667:0x01020408 ODT chip select 3 map for reads. Determines which chip(s) will have termination when a read occurs on chip 3. ODT chip select 2 map for reads. Determines which chip(s) will have termination when a read occurs on chip 2. ODT chip select 1 map for reads. Determines which chip(s) will have termination when a read occurs on chip 1. ODT chip select 0 map for reads. Determines which chip(s) will have termination when a read occurs on chip 0.
ODT_RD_MAP_CS3
27:24
0x0
0x0-0xf
ODT_RD_MAP_CS2
19:16
0x0
0x0-0xf
ODT_RD_MAP_CS1
11:8
0x0
0x0-0xf
ODT_RD_MAP_CS0
3:0
0x0
0x0-0xf
CONF_CTL_08[63:32]
Offset: 0x80
DDR2 667:0x01020408 ODT chip select 3 map for writes. Determines which chip(s) will have termination when a write occurs on chip 3.
ODT_WR_MAP_CS3
59:56
0x0
0x0-0xf
27/48
DDR2 SDRAM controller interface description Table 12.
STLS2F01
DDR SDRAM configuration parameter register format (continued)
Parameters Bits Default value Range Description ODT chip select 2 map for writes. Determines which chip(s) will have termination when a write occurs on chip 2. ODT chip select 1 map for writes. Determines which chip(s) will have termination when a write occurs on chip 1. ODT chip select 0 map for writes. Determines which chip(s) will have termination when a write occurs on chip 0.
ODT_WR_MAP_CS2
51:48
0x0
0x0-0xf
ODT_WR_MAP_CS1
43:40
0x0
0x0-0xf
ODT_WR_MAP_CS0
35:32
0x0
0x0-0xf
CONF_CTL_09[31:0]
Offset: 0x90 27:24 0x0
DDR2 667:0x00000000 0x0-0xf Port number of command that caused the PORT data error. Readonly Type of error and access type that caused the PORT command error. Read-only) Port number of command that caused the PORT command error. Read-only Source ID of command that caused an Out-of-Range interrupt. Readonly
PORT_DATA_ERROR_ID
PORT_CMD_ERROR_TYPE
19:16
0x0
0x0-0xf
PORT_CMD_ERROR_ID
11:8
0x0
0x0-0xf
OUT_OF_RANGE_SOURCE_I D CONF_CTL_09[63:32]
3:0
0x0
0x0-0xf
Offset: 0x90 60:56 52:48 43:40 35:32 Offset: 0xa0 29:24 20:16 12:8 4:0 Offset: 0xa0 62:56 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
DDR2 667:0x0000050b 0x0-0x1f 0x0-0x1f 0x0-0xf 0x0-0xf OCD pull-up adjust setting for DRAMs for chip select 0. OCD pull-down adjust setting for DRAMs for chip select 0. DRAM TRP parameter in cycles. DRAM TDAL parameter in cycles.
OCD_ADJUST_PUP_CS0 OCD_ADJUST_PDN_CS0 TRP TDAL CONF_CTL_10[31:0] AGE_COUNT TRC TMRD TFAW CONF_CTL_10[63:32]
DDR2 667:0x3f130200 0x0-0x3f Initial value of master aging-rate counter for command aging.
0x0-0x1f DRAM TRC parameter in cycles. 0x0-0x1f DRAM TMRD parameter in cycles. 0x0-0x1f DRAM TFAW parameter in cycles. DDR2 667:0x1d1d1d3f Fraction of a cycle to delay the DQS 0x0-0x7f signal from the DRAMs for dll_rd_dqs_slice 2 during reads.
DLL_DQS_DELAY_2
28/48
STLS2F01 Table 12.
DDR2 SDRAM controller interface description DDR SDRAM configuration parameter register format (continued)
Parameters Bits Default value 0x0 Range Description
DLL_DQS_DELAY_1
54:48
Fraction of a cycle to delay the DQS 0x0-0x7f signal from the DRAMs for dll_rd_dqs_slice 1 during reads. Fraction of a cycle to delay the DQS 0x0-0x7f signal from the DRAMs for dll_rd_dqs_slice 0 during reads. 0x0-0x3f Initial value of individual command aging counters for command aging.
DLL_DQS_DELAY_0
46:40
0x0
COMMAND_AGE_COUNT CONF_CTL_11[31:0]
37:32
0x0
Offset: 0xb0 30:24 0x0
DDR2 667:0x1d1d1d1d Fraction of a cycle to delay the DQS 0x0-0x7f signal from the DRAMs for dll_rd_dqs_slice 6 during reads. Fraction of a cycle to delay the DQS 0x0-0x7f signal from the DRAMs for dll_rd_dqs_slice 5 during reads. Fraction of a cycle to delay the DQS 0x0-0x7f signal from the DRAMs for dll_rd_dqs_slice 4 during reads. Fraction of a cycle to delay the DQS 0x0-0x7f signal from the DRAMs for dll_rd_dqs_slice 3 during reads. DDR2 667:0x507f1d1d 0x0 0x0-0x7f Fraction of a cycle to delay the clk_wr signal in the controller.
DLL_DQS_DELAY_6
DLL_DQS_DELAY_5
22:16
0x0
DLL_DQS_DELAY_4
14:8
0x0
DLL_DQS_DELAY_3 CONF_CTL_11[63:32] WR_DQS_SHIFT
6:0
0x0
Offset: 0xb0 62:56
DQS_OUT_SHIFT
54:48
0x0
Fraction of a cycle to delay the write 0x0-0x7f DQS signal to the DRAMs during writes. Fraction of a cycle to delay the DQS 0x0-0x7f signal from the DRAMs for dll_rd_dqs_slice 8 during reads. Fraction of a cycle to delay the DQS 0x0-0x7f signal from the DRAMs for dll_rd_dqs_slice 7 during reads. DDR2 667:0x0e000000
DLL_DQS_DELAY_8
46:40
0x0
DLL_DQS_DELAY_7 CONF_CTL_12[31:0] TRAS_MIN OUT_OF_RANGE_LENGTH ECC_U_SYND ECC_C_SYND CONF_CTL_12[63:32]
38:32
0x0
Offset: 0xc0 31:24 23:16 15:8 7:0 Offset: 0xc0 0x0 0x0 0x0 0x0
0x0-0xff 0x0-0xff 0x0-0xff 0x0-0xff
DRAM TRAS_MIN parameter in cycles. Length of command that caused an Out-of-Range interrupt. Read-only. Syndrome for uncorrectable ECC event. Read-only. Syndrome for correctable ECC event. Read-only.
DDR2 667:0x002a3305
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DDR2 SDRAM controller interface description Table 12.
STLS2F01
DDR SDRAM configuration parameter register format (continued)
Parameters Bits Default value Range Description
DLL_DQS_DELAY_BYPASS_0
56:48
0x0
Number of delay elements to include in the DQS signal from the DRAMs 0x0-0x1ff for dll_rd_dqs_slice 0 during reads when DLL is being bypassed. 0x0-0xff 0x0-0xff DRAM TRFC parameter in cycles. DRAM TRCD parameter in cycles.
TRFC TRCD_INT CONF_CTL_13[31:0]
47:40 39:32 Offset: 0xd0
0x0 0x0
DDR2 667:0x002a002a Number of delay elements to include in the DQS signal from the DRAMs for dll_rd_dqs_slice 2 during reads when DLL is being bypassed. Number of delay elements to include in the DQS signal from the DRAMs for dll_rd_dqs_slice 1 during reads when DLL is being bypassed.
DLL_DQS_DELAY_BYPASS_2
24:16
0x0
0x0-0x1
DLL_DQS_DELAY_BYPASS_1
8:0
0x0
0x0-0x1
CONF_CTL_13[63:32]
Offset: 0xd0
DDR2 667:0x002a002a Number of delay elements to include in the DQS signal from the DRAMs 0x0-0x1ff for dll_rd_dqs_slice 4 during reads when DLL is being bypassed. Number of delay elements to include in the DQS signal from the DRAMs 0x0-0x1ff for dll_rd_dqs_slice 3 during reads when DLL is being bypassed. DDR2 667:0x002a002a Number of delay elements to include in the DQS signal from the DRAMs 0x0-0x1ff for dll_rd_dqs_slice 6 during reads when DLL is being bypassed. Number of delay elements to include in the DQS signal from the DRAMs 0x0-0x1ff for dll_rd_dqs_slice 7 during reads when DLL is being bypassed. DDR2 667:0x002a002a Number of delay elements to include in the DQS signal from the DRAMs 0x0-0x1ff for dll_rd_dqs_slice 8 during reads when DLL is being bypassed. Number of delay elements to include in the DQS signal from the DRAMs 0x0-0x1ff for dll_rd_dqs_slice 7 during reads when DLL is being bypassed. DDR2 667:0x00000004
DLL_DQS_DELAY_BYPASS_4
56:48
0x0
DLL_DQS_DELAY_BYPASS_3
40:32
0x0
CONF_CTL_14[31:0]
Offset: 0xe0
DLL_DQS_DELAY_BYPASS_6
24:16
0x0
DLL_DQS_DELAY_BYPASS_5
8:0
0x0
CONF_CTL_14[63:32]
Offset: 0xe0
DLL_DQS_DELAY_BYPASS_8
56:48
0x0
DLL_DQS_DELAY_BYPASS_7
40:32
0x0
CONF_CTL_15[31:0]
Offset: 0xf0
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STLS2F01 Table 12.
DDR2 SDRAM controller interface description DDR SDRAM configuration parameter register format (continued)
Parameters DLL_LOCK Bits 24:16 Default value 0x0 Range 0x0-0x1ff Description Number of delay elements in master DLL lock. Read-only
DLL_INCREMENT CONF_CTL_15[63:32]
8:0 Offset: 0xf0
0x0
Number of elements to add to 0x0-0x1ff DLL_START_POINT when searching for lock. DDR2 667:0x00b4000a Number of delay elements to include in the write DQS signal to the 0x0-0x1ff DRAMs during writes when DLL is being bypassed. 0x0-0x1ff Initial delay count when searching for lock in master DLL.
DQS_OUT_SHIFT_BYPASS
56:48
0x0
DLL_START_POINT CONF_CTL_16[31:0] INT_ACK
40:32
0x0
Offset: 0x100 25:16 0x0
DDR2 667:0x00000087 0x0-0x3ff Clear mask of the INT_STATUS parameter. Write-only.
WR_DQS_SHIFT_BYPASS CONF_CTL_16[63:32] INT_STATUS INT_MASK CONF_CTL_17[31:0] EMRS1_DATA TREF CONF_CTL_17[63:32] EMRS2_DATA_1 EMRS2_DATA_0 CONF_CTL_18[31:0] EMRS2_DATA_3 EMRS2_DATA_2 CONF_CTL_18[63:32]
8:0
0x0
Number of delay elements to include 0x0-0x1ff in the clk_wr signal in the controller when DLL is being bypassed. DDR2 667:0x00000000
Offset: 0x100 58:48 42:32 Offset: 0x110 30:16 13:0 Offset: 0x110 62:48 0x0000 46:32 0x0000 Offset: 0x120 30:16 0x0000 14:0 Offset: 0x120 0x0000 0x0 0x0 0x0 0x0
0x0-0x7ff 0x0-0x7ff
Status of interrupt features in the controller. Read-only. Mask for controller_int signals from the INT_STATUS parameter.
DDR2 667:0x0000181b 0x0-0x7ff EMRS1 data. 0x0-0x3ff DRAM TREF parameter in cycles. DDR2 667:0x00000000 0x00x7fff 0x00x7fff EMRS2 data for chip select 1. EMRS2 data for chip select 0.
DDR2 667:0x00000000 0x00x7fff 0x00x7fff EMRS2 data for chip select 3. EMRS2 data for chip select 2.
DDR2 667:0x001c0000 Allow narrow instructions from port 0 requestors with bit enabled.
AXI0_EN_SIZE_LT_WIDTH_IN STR
63:48 0x0000 0x0-0xffff
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DDR2 SDRAM controller interface description Table 12.
STLS2F01
DDR SDRAM configuration parameter register format (continued)
Parameters Bits Default value Range 0x00x7fff Description EMRS3 data.
EMRS3_DATA CONF_CTL_19[31:0] TDLL TCPD CONF_CTL_19[63:32] TRAS_MAX TPDEX CONF_CTL_20[31:0] TXSR TXSNR CONF_CTL_20[63:32]
46:32 0x0000 Offset: 0x130
DDR2 667:0x00c8006b
31:16 0x0000 0x0-0xffff DRAM TDLL parameter in cycles. 15:0 Offset: 0x130 0x0000 0x0-0xffff DRAM TCPD parameter in cycles. DDR2 667:0x48e10002 DRAM TRAS_MAX parameter in cycles.
63:48 0x0000 0x0-0xffff
47:32 0x0000 0x0-0xffff DRAM TPDEX parameter in cycles. Offset: 0x140 DDR2 667:0x00c8002f
31:16 0x0000 0x0-0xffff DRAM TXSR parameter in cycles. 15:0 Offset: 0x140 0x0000 0x0-0xffff DRAM TXSNR parameter in cycles. DDR2 667:0x00000000 Value to XOR with generated ECC codes for forced write check. Controller version number. Readonly.
XOR_CHECK_BITS VERSION CONF_CTL_21[31:0]
63:48 0x0000 0x0-0xffff 47:32 0x2041 0x2041
Offset: 0x150 31:24 0x0000 23:0 Offset: 0x150 60:32 0x0 0x0000
DDR2 667:0x00000036 0x0Address of correctable ECC event. 0x1ffffffff Read-only. 0x00xfffff DRAM TINIT parameter in cycles.
ECC_C_ADDR[7:0] TINIT CONF_CTL_21[63:32]
DDR2 667:0x00000000 0x0Address of correctable ECC event. 0x1ffffffff Read-only. DDR2 667:0x00000000 0x0 0x0Address of uncorrectable ECC event. 0x1ffffffff Read-only. DDR2 667:0x00000000 0x0 0x0Address of uncorrectable ECC event. 0x1ffffffff Read-only. DDR2 667:0x00000000 0x0 0x0Address of command that caused an 0x1ffffffff Out-of-Range interrupt. Read-only DDR2 667:0x00000000 0x0 0x0Address of command that caused an 0x1ffffffff Out-of-Range interrupt. Read-only. DDR2 667:0x00000000
ECC_C_ADDR[36:8] CONF_CTL_22[31:0]
Offset: 0x160 31:0
ECC_U_ADDR[31:0] CONF_CTL_22[63:32]
Offset: 0x160 36:32
ECC_U_ADDR[36:32] CONF_CTL_23[31:0]
Offset: 0x170 31:0
OUT_OF_RANGE_ADDR[31:0] CONF_CTL_23[63:32]
Offset: 0x170
OUT_OF_RANGE_ADDR[36:32] 36:32 CONF_CTL_24[31:0] Offset: 0x180
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STLS2F01 Table 12.
DDR2 SDRAM controller interface description DDR SDRAM configuration parameter register format (continued)
Parameters PORT_CMD_ERROR_ADDR[31 :0] CONF_CTL_24[63:32] Bits 31:0 Default value 0x0 Range Description
0x0Address of port that caused the 0x1ffffffff PORT command error. Read-only. DDR2 667:0x00000000
Offset: 0x180 0x0
PORT_CMD_ERROR_ADDR[36 36:32 :32] CONF_CTL_25[31:0] Offset: 0x190 31:0
0x0Address of port that caused the 0x1ffffffff PORT command error. Read-only DDR2 667:0x00000000
ECC_C_DATA[31:0] CONF_CTL_25[63:32]
0x0
0x0Data associated with correctable 0x1ffffffff ECC event. Read-only. DDR2 667:0x00000000
Offset: 0x190 63:32 0x0
ECC_C_DATA[63:32] CONF_CTL_26[31:0]
0x0Data associated with correctable 0x1ffffffff ECC event. Read-only. DDR2 667:0x00000000
Offset: 0x1a0 31:0 0x0
ECC_U_DATA[31:0] CONF_CTL_26[63:32]
0x0Data associated with uncorrectable 0x1ffffffff ECC event. Read-only. DDR2 667:0x00000000
Offset: 0x1a0 63:32 0x0
ECC_U_DATA[63:32] CONF_CTL_27[63:32] CKE_DELAY CONF_CTL_28[63:32] UB_DIMM
0x0Data associated with uncorrectable 0x1ffffffff ECC event. Read-only. DDR2 667:0x00000000
Offset: 0x1b0 2:0 Offset: 0x1c0 0:0 0x0 0x0
0x0-0x7
Additional cycles to delay CKE for status reporting.
DDR2 667:0x00000001 0x0-0x1 Enable unbuffered DIMM.
Note: 1. CONF_CTL_00 AP The parameter determines whether the auto pre-charge function is enabled. Once the function is enabled, memory will close the page, after each write/read instruction. If mass continuous address operation happens, the parameter will caused the performance degradation. CONF_CTL_00 CONCURRENTAP The parameter determines whether the concurrent auto pre-charge function is enabled. Most of SDRAM vendors do not support this feature. CONF_CTL_03 SREFRESH The parameter is used set the self-refresh style. It must be set 0, when returning from self-refresh. CONF_CTL_07 CASLAT_LIN_GATE The parameter is used to control the data sample of memory controller when read
2.
3.
4.
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DDR2 SDRAM controller interface description
STLS2F01
operation returns. In general, It is equal to or less than half period of ACALAT_LIN. The Value of CASLAT_LIN is twice of the one of CAS. 5. 6. CONF_CTL_15 DLL_INCREMENT The parameter should not be set 0. CONF_CTL_15 DLL_START_POINT The parameter should not be set 0/1 and should be less than the 1.5 times of DLL_LOCK_VALUE. CONF_CTL_28 UB_DIMM The parameter should be set 1, when unbuffered DIMM(s) are used. It should be set 0, when the SDRAM(s) are used.
7.
4.5
DDR2 SDRAM sample mode configuration
DDR2 SDRAM controller is integrated in the STLS2F01. And the delay compensation circuit (using DLL) is used to sample return data of DQS. Since there is the delay of data return path between the memory controller and SDRAM module, it is necessary to introduce a set of control signals used to measure the delay. The control signals of DDR2_GATE_I[3:0] and DDR2_GATE_O[3:0] are used to the delay measurement. On the PCB, DDR2_GATE_I and DDR2_GAT_O are connected together to imitate the wiring delay on the PCB. Thus, the accuracy of sampling can be guaranteed.
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STLS2F01
Initialization process
5
Initialization process
The initialization of STLS2F01 is divided into core part and interface part. When STLS2F01 PCI interface is configured as main bridge, interface initialization is finished internally. And PCI_RESETn is output signal. When the processor works as PCI/PCI-X devices used in other system, PCI_RESETn acts as input to reset the PCI interface of STLS2F01. When processor reset signal SYSRESETn is low, related clock, test signals and initial signals must be valid.

SYSCLK, MEMCLK, CLKSEL and PCI_CLK must be stable Initial signal PCI_CONFIG should set to appropriate value TEST_CTRL[7:0] are all high
When SYSRESETn is invalid, the processor internal reset logic begins to work to initialize the chip. The SYSRESETn should be valid at least one clock cycle to ensure it can be sampled by reset logic. The work-mode of PCI bus is decided by main bridge during reset period. As such, PCI_RESETn output generated by processor when it works as main bridge will be used to ensure all devices working at the same mode. When not in main bridge mode, PCI_RESETn input will be used to receive bus configuration.
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Initialization process Figure 9. Initialization process when in main bridge mode
SYSCLK
STLS2F01
MEMCLK
PCI_CLK
PCICONFIG
TESTCTRL
SYSRESETn
PCI_RESETn
1ms
64K SYSCLK
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STLS2F01
Electrical characteristics
6
6.1
Electrical characteristics
Absolute maximum rating
Stresses above the absolute maximum ratings listed in Table 13 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended period may affect device reliability. Table 13. Absolute maximum rating.
Description CPU core voltage DDR2 voltage IO voltage DDR2 voltage reference 1.0V PLL1 digital voltage 1.0V PLL0 digital voltage 1.8V PLL IO voltage 1.8V PLL1 analog voltage 1.8V PLL0 analog voltage 1.2V PLL IO voltage Storage Temperature Min 1.2 1.7 3.0 0.83 0.9 0.9 1.7 1.7 1.7 0.9 Max 1.3 1.9 3.6 0.97 1.3 1.3 1.9 1.9 1.9 1.3 Unit V V V V V V V V V V C
Parameter vdd vdde1v8 vdde3v3 DDR2_VREF pll_vdd_1 pll_vdd_0 pllio_vdde1v8 pll_vdde1v8_1 Pll_vdde1v8_0 pllio_vdd TS
6.2
Recommended operation environment
Table 14. Recommended operating temperature, voltage supply and frequency
Description Operating Temperature CPU core voltage DDR2 voltage I/O voltage DDR2 voltage reference 1.0V PLL1 digital voltage 1.0V PLL0 digital voltage 1.8V PLL I/O voltage 1.8V PLL1 analog voltage 1.8V PLL0 analog voltage 1.2V PLL I/O voltage Min 0 1.25 1.8 3.3 0.9 1.2 1.2 1.8 1.8 1.8 1.2 Typ Max 85 Unit C V V V V V V V V V V Parameter TA vdd Vdde1v8 vdde3v3 DDR2_VREF pll_vdd_1 pll_vdd_0 pllio_vdde1v8 pll_vdde1v8_1 Pll_vdde1v8_0 pllio_vdd
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Electrical characteristics
STLS2F01
6.3
DC parameters
Table 15.
Parameter VIH VIL VOH VOL IIH IIL IOL IOH CIN COUT RPH
DC parameters
Description Input high level voltage input low level voltage output high level voltage output low level voltage input high level leakage current input low level leakage current output low level current output high level current Input pin capacitor Output pin capacitor Pull-up resistance 4.4 23 32 0.002 -67.3 8 8 7 25 50 7.5 27 81 0.8 vdde3v3-0.3 0.3 0.4 -65 Min Typ Max 2 Unit V V V V A A mA mA pF pF K
(5)
Note
(1) (1) (2) (2) (3) (3) (4) (4)
1. Input pin level (including tri-state pin). 2. Individual output pin (including output state tri-state pin) level. 3. For tri-state input pin (excluding input). 4. Individual output pin (including output state tri-state pin) driving capability. 5. For input pin (excluding tri-state pin).
Table 16.
Parameter CTIN CTOUT CTCK
DC parameters (JTAG)
Description Test input capacitance Test output capacitance TCK capacitance Min 4.4 23 4.4 Typ 7 25 7 Max 7.5 27 7.5 Unit pF pF pF Note
(1) (2)
1. For TDI, TMS and TRST in JTAG. 2. For TDO in JTAG.
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STLS2F01
Electrical characteristics
6.4
AC parameters
Table 17. Clock parameters (Test Conditions: SYSCLK=100 MHz, PCICLK=133 MHz, MEMCLK=333 MHz, CoreClk=1000 MHz)
Parameter SYSCLK High Level Time SYSCLK Low Level Time SYSCLK Rising Time SYSCLK Falling Time SYSCLK Cycle Variation PCI_CLK High Level Time PCI_CLK Low Level Time PCI_CLK Rising Slew PCI_CLK Falling Slew PCI_CLK Cycle Variation MEMCLK High Level Time MEMCLK Low Level Time MEMCLK Rising Slew MEMCLK Falling Slew MEMCLK Cycle Variation DQS High Level Time DQS Low Level Time DQS Rising Slew DQS Falling Slew DQS Cycle Variation 1.35 1.35 1 1 225 1.41 1.41 1 1 225 1.65 1.65 3 3 1.5 1.5 500 1.59 1.59 Min 2 2 1 1 Typ 5 Max 8 8 1 1 300 Unit ns ns ns ns ps ns ns V/ns V/ns ps ns ns V/ns V/ns ps ns ns V/ns V/ns ps
Table 18.
Input setup and hold time (Test Conditions: SYSCLK=100 MHz, PCICLK=133 MHz, MEMCLK=333 MHz, CoreClk=1000 MHz)
Parameter Min 1.2 0.5 1.2 0.5 0.1 0.175 Tpy Max Unit ns ns ns ns ns ns
PCI_* Signals Setup Time PCI_* Signals Hold Time LIO_* Signals Setup Time LIO_* Signals Hold Time DDR2_DQ*/CB* Signals Setup Time DDR2_DQ*/CB* Signals Hold Time
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Electrical characteristics Table 19.
STLS2F01
Input setup and hold time (Test Conditions: SYSCLK=100 MHz, PCICLK=66 MHz, CoreClk=1000 MHz)
Parameter Min 3.0 0.0 3.0 0.0 Tpy Max Unit ns ns ns ns
PCI_* Signals Setup Time PCI_* Signals Hold Time LIO_* Signals Setup Time LIO_* Signals Hold Time
Table 20.
Output delay time (Test Conditions: SYSCLK=100 MHz, PCICLK=133 MHz, CoreClk=1000 MHz)
Parameter Min 0.7 1.5 1.5 0.75 Typ Max 3.8 6.0 Unit ns ns ns ns
PCI_* Signals Effective Delay LIO_* Signals Effective Delay DDDR2_A*/RAS*/CAS*/WE*/CS*/CKE*/ODT* Signals Effective Delay DDR2_DQ*/DQM* Effective Delay
Table 21.
JTAG parameters (Test Condition: TCK = 100 MHz)
Parameter Min 2 2 1 1 10 3.5 2.5 4.4 5.5 1.28 1.28 Typ 5 Max 8 8 1 1 Unit ns ns ns ns ns ns ns ns ns
TCK high level time TCK low level time TCK rising time TCK falling time TRST pulse width TDI,TMS setup time TDI,TMS hold time TDO output effective delay TDO output disable delay
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STLS2F01
Thermal characteristics
7
7.1
Thermal characteristics
Thermal resistivity
Heat spreader optimized with the following assumptions

Ambient temperature 40 C Package assembled on PCB as per JEDEC EIA/JESD51-9 Max power 7.45 W
Customer should implement power extraction from the top of the package so that package case to ambient Rth is below 16 C/W. Without air flow, this can be achieved with a 40x40x15 heat spreader or 27x27x25 HS or 35x35x18 HS. This should guarantee 120 C max junction temperature (low margin). The preferred configuration is to use a 27x27x10 HS with 0.5m/s air flow. A single fan in PC case should be enough. In such case, max Junction temp should be around 112 C.
7.2
Reflow temperature to time curve
The STLS2F01 processor uses a flip-chip eutectic packaging technology. It can endure maximum reflow temperature ranging from 235 C to 245 C. The reflow temperature curve and parameters are showed in Figure 10 and Table 22.
Figure 10. Reflow temperature to time curve
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Thermal characteristics Table 22. Reflow temperature parameters
Parameter A B C D E F F-1 Value 120 ~ 180 90 ~ 120 0.3 ~ 2.0 235 ~ 245 85 ~ 105 < 1.2 < 1.0
STLS2F01
Unit C sec C/sec C sec C/sec C/sec
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STLS2F01
Pin arrangement and package information
8
8.1
Pin arrangement and package information
Pin arrangement
The STLS2F01 processor is packaged in HFCBGA452. The pin arrangement is showed in Figure 11, and Figure 13,
Figure 11. Pin arrangement (left-hand side)
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF gnde vdd vdd TEST_CTRL0 pll_vdd_1 pllio_vdde1v8 gpio1 vdd vdd CLKSEL7 CLKSEL6 CLKSEL3 vdd vdd PCI_CONFIG3 PCI_CONFIG2 PCI_AD01 PCI_CBEn0 PCI_AD10 GND PCI_AD15 PCI_PERR PCI_TRDYn vdd vdd gnde 1 vdd gnde TEST_CTRL3 TEST_CTRL1 gpio0 pll_gnd_1 pllio_gnd pll_gnde_0 gnde pll_vdd_0 CLKSEL5 CLKSEL4 CLKSEL1 PCI_CONFIG5 PCI_CONFIG0 PCI_IDSEL PCI_AD03 PCI_AD06 PCI_AD09 PCI_AD11 PCI_PAR PCI_STOPn PCI_DEVSELn PCI_CBEn2 gnde vdd 2 2 3 TEST_CTRL7 TEST_CTRL5 gnde TEST_CTRL2 gpio2 pll_vdde1v8_1 pllio_vdd gnde pll_gnd_0 gnde CLKSEL8 CLKSEL0 PCI_CONFIG7 PCI_CONFIG4 PCI_CONFIG1 PCI_AD00 PCI_AD05 PCI_AD07 PCI_AD12 PCI_AD13 PCI_SERR PCI_IRDYn vdd gnde PCI_AD16 vdd 3 gnde PCI_AD17 PCI_AD18 PCI_AD20 4 4 LIO_AD01 TEST_CTRL6 memclk gnde gpio3 pll_gnde_1 pllio_gnde gnde pll_vdde1v8_0 gnde CLKSEL9 CLKSEL2 PCI_CONFIG6 vdde3v3 vdde3v3 PCI_AD02 PCI_AD04 PCI_AD08 PCI_AD14 PCI_CBEn1 PCI_FRAMEn VDD PCI_AD19 PCI_AD23 PCI_AD21 PCI_CBEn3 5 PCI_AD22 PCI_AD24 PCI_AD26 PCI_AD25 6 PCI_AD28 PCI_AD27 PCI_AD31 PCI_AD29 7 PCI_AD30 PCI_GNTn6 PCI_REQn6 PCI_REQn4 8 PCI_GNTn5 PCI_REQn5 PCI_GNTn3 PCI_GNTn4 9 J K L M N P R T U V gnde gnde vdd vdd vdd vdd vdd vdd gnde gnde 9 9 5 LIO_AD04 LIO_AD05 SYSRESETN pllclock1 6 LIO_AD12 LIO_AD08 LIO_AD06 LIO_AD02 7 LIO_A3 LIO_A1 LIO_AD14 LIO_AD10 8 LIO_A5 LIO_A4 LIO_A0 LIO_AD09 9 LIO_A7 sysclk testclk pllclock0
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Pin arrangement and package information Figure 12. Pin arrangement (middle)
10 TEST_CTRL4 LIO_AD00 LIO_AD03 LIO_AD11 11 LIO_AD07 LIO_AD15 LIO_AD13 LIO_CSn 12 LIO_A2 LIO_A6 LIO_RDn LIO_WRn 13 LIO_ADLOCK LIO_DIR LIO_DEN LIO_ROMCSn 14 DDR2_VREF DDR2_DQ00 DDR2_DQ04 DDR2_DQ01 15 DDR2_DQSn0 DDR2_DQSp0 DDR2_DQ05 DDR2_DQM0 16 DDR2_DQ03 DDR2_DQ02 DDR2_DQ06 DDR2_DQ07 17 DDR2_DQ12 DDR2_DQ09 DDR2_DQ08 DDR2_DQ13 18
STLS2F01
DDR2_DQM1 DDR2_DQSp1 DDR2_DQSn1 DDR2_GATEI0
A B C D E F G
10 vdd gnde vdde3v3 vdde3v3 vdde3v3 vdde3v3 vdde3v3 vdde3v3 vdde3v3 gnde 10 vdd
11 vdd
12 gnde
13 gnde
14 gnde
15
16 vdde1v8 vdde1v8 vdde1v8 gnd gnd gnd gnd vdde1v8 vdde1v8 vdde1v8
17 vdde1v8 vdde1v8 vdde1v8 vdde1v8 vdde1v8 vdde1v8 vdde1v8 vdde1v8 vdde1v8 vdde1v8 17 gnde gnde
18
H J K L M N P R T U V
vdde3v3 vdde3v3 gnd gnd gnd gnd vdde3v3 vdde3v3 vdd 11
vdde3v3 vdde3v3 gnd gnd gnd gnd vdde3v3 vdde3v3 vdd 12
vdde3v3 gnd gnd gnd gnd gnd gnd vdde3v3 vdde3v3 13
vdde1v8 gnd gnd gnd gnd gnd gnd vdde1v8 gnde 14
vdde1v8 vdde1v8 gnd gnd gnd gnd vdde1v8 vdde1v8 gnde 15
vdde1v8 gnde gnde gnde gnde vdde1v8 gnde gnde 18
16
W Y AA AB
PCI_REQn3 PCI_REQn2 PCI_GNTn2 PCI_REQn1 10
PCI_GNTn1 PCI_REQn0 PCI_GNTn0 PCI_RESETn 11
PCI_IRQnA PCI_IRQnC PCI_IRQnB PCI_IRQnD 12
INTN1 INTN2 INTN3 NMIN 13
tck tdo trst INTN0 14
comp1v8_resistor PCI_CLK tms tdi 15
DDR2_SCSn1 DDR2_ODT3 DDR2_ODT1 comp1v8_gnd 16
DDR2_A00 DDR2_SCSn3 DDR2_A01 DDR2_A02 17
DDR2_ODT0 DDR2_ODT2 DDR2_CASn DDR2_A13 18
AC AD AE AF
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STLS2F01 Figure 13. Pin arrangement (right-hand side)
19 DDR2_GATEO0 DDR2_DQ14 DDR2_DQ15 DDR2_DQ11 20 DDR2_DQM2 DDR2_DQ16 DDR2_DQ10 DDR2_DQ21 21 DDR2_DQ20 DDR2_DQ17 DDR2_DQSp2 DDR2_DQSn2 22 DDR2_DQ22 DDR2_DQ23 DDR2_DQ18 DDR2_DQ19 23 DDR2_CKE3 DDR2_CKn4 DDR2_CKp4 gnde DDR2_A14 DDR2_A08 DDR2_A09 DDR2_DQM3 J K L M N P R T U V DDR2_DQ30 DDR2_DQ27 DDR2_DQ37 DDR2_DQ39 DDR2_DQ34 DDR2_BA1
Pin arrangement and package information
24 vdde1v8 DDR2_CKE1 gnde DDR2_CKn1 DDR2_A07 DDR2_CKE0 DDR2_A03 DDR2_DQ25 DDR2_DQ36 DDR2_DQ26 DDR2_DQ33 DDR2_DQ38 DDR2_DQ35 DDR2_A10 DDR2_SCSn0 DDR2_DQ40 DDR2_DQSn5 DDR2_DQ47 DDR2_DQ49 DDR2_DQ51 DDR2_DQ53 DDR2_DQ60 DDR2_DQSp7 gnde DDR2_DQ63 vdde1v8 24
25 vdde1v8 gnde DDR2_CKE2 DDR2_CKp1 DDR2_A11 DDR2_A05 DDR2_DQ29 DDR2_DQ24 DDR2_DQSn3 DDR2_GATEO1 DDR2_DQ32 DDR2_DQSn4 DDR2_CKp3 DDR2_CKn0 DDR2_BA0 DDR2_DQ45 DDR2_DQSp5 DDR2_DQ42 DDR2_GATEI2 DDR2_DQSp6 DDR2_DQ54 DDR2_DQM7 DDR2_DQSn7 DDR2_DQ62 gnde vdde1v8 25 gnde
26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 26
vdde1v8 DDR2_A12 DDR2_BA2 DDR2_A06 DDR2_A04 DDR2_DQ28 DDR2_DQ31 DDR2_DQSp3 DDR2_GATEI1 DDR2_DQM4 DDR2_DQSp4 DDR2_CKn3 DDR2_CKp0 DDR2_RASn DDR2_DQ41 DDR2_DQM5 DDR2_DQ46 DDR2_GATEO2 DDR2_DQSn6 DDR2_DQ50 DDR2_DQ56 DDR2_DQ57 DDR2_DQ58 vdde1v8 gnde
DDR2_SCSn2 DDR2_DQ44 DDR2_DQ43 DDR2_DQ48 DDR2_DQ52 DDR2_DQ55 DDR2_DQM6 DDR2_DQ61
DDR2_WEn DDR2_CKp2 DDR2_CKn2 DDR2_CKn5 19
DDR2_CB2 DDR2_CB3 DDR2_CB7 DDR2_CKp5 20
DDR2_DQM8 DDR2_CB6 DDR2_DQSp8 DDR2_DQSn8 21
DDR2_GATEI3 DDR2_GATEO3 DDR2_CB5 DDR2_CB1 22
gnde DDR2_DQ59 DDR2_CB4 DDR2_CB0 23
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Package information
STLS2F01
9
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 14. HFCBGA452 mechanical data & package dimensions
mm DIM. MIN. A A1 A3 A4 b D D1 E E1 e F aaa ddd eee fff 0.450 0.250 1.300 1.000 0.500 TYP. MAX. 3.150 0.0098 0.0512 0.0394 0.550 0.0177 0.0197 0.0217 MIN. TYP. MAX. 0.1240 inch
OUTLINE AND MECHANICAL DATA
26.800 27.000 27.200 1.0551 1.0630 1.0709 25.000 0.9843
26.800 27.000 27.200 1.0551 1.0630 1.0709 25.000 1.000 1.000 0.200 0.200 0.250 0.100 0.9843 0.0394 0.0394 0.0079 0.0079 0.0098 0.0039
HFCBGA452 (27x27x2.9mm)
Heat Spreader Flip Chip Ball Grid Array
8061758 A
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STLS2F01
Revision history
10
Revision history
Table 23.
Date 30-May-2008
Document revision history
Revision 1 Initial relase. Changes
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STLS2F01
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